ARM: Pull some SkyEye fixes from 3dmoo.
This commit is contained in:
bunnei
parent
af1cd769e7
commit
d26b7146ce
3 changed files with 485 additions and 419 deletions
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@ -1166,7 +1166,7 @@ mainswitch:
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else if ((((int)BITS(21, 27)) == 0x3e) && ((int)BITS(4, 6) == 0x1)) {
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//(ARMword)(instr<<(31-(n))) >> ((31-(n))+(m))
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unsigned msb ,tmp_rn, tmp_rd, dst;
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msb = tmp_rd = tmp_rn = dst = 0;
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tmp_rd = tmp_rn = dst = 0;
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Rd = BITS(12, 15);
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Rn = BITS(0, 3);
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lsb = BITS(7, 11);
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@ -1737,7 +1737,7 @@ mainswitch:
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//chy 2006-02-15 if in user mode, can not set cpsr 0:23
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//from p165 of ARMARM book
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state->Cpsr = GETSPSR (state->Bank);
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//ARMul_CPSRAltered (state);
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ARMul_CPSRAltered (state);
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#else
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rhs = DPRegRHS;
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temp = LHS & rhs;
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@ -1877,7 +1877,7 @@ mainswitch:
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/* TEQP reg */
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#ifdef MODE32
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state->Cpsr = GETSPSR (state->Bank);
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//ARMul_CPSRAltered (state);
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ARMul_CPSRAltered (state);
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#else
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rhs = DPRegRHS;
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temp = LHS ^ rhs;
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@ -1993,7 +1993,7 @@ mainswitch:
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/* CMPP reg. */
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#ifdef MODE32
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state->Cpsr = GETSPSR (state->Bank);
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//ARMul_CPSRAltered (state);
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ARMul_CPSRAltered (state);
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#else
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rhs = DPRegRHS;
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temp = LHS - rhs;
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@ -2112,7 +2112,7 @@ mainswitch:
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if (DESTReg == 15) {
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#ifdef MODE32
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state->Cpsr = GETSPSR (state->Bank);
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//ARMul_CPSRAltered (state);
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ARMul_CPSRAltered (state);
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#else
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rhs = DPRegRHS;
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temp = LHS + rhs;
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@ -2200,17 +2200,57 @@ mainswitch:
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Handle_Store_Double (state, instr);
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break;
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}
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if (BITS(4, 11) == 0xF9) { //strexd
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u32 l = LHSReg;
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bool enter = false;
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if (state->currentexval == (u32)ARMul_ReadWord(state, state->currentexaddr)&&
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state->currentexvald == (u32)ARMul_ReadWord(state, state->currentexaddr + 4))
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enter = true;
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//todo bug this and STREXD and LDREXD http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0360e/CHDGJGGC.html
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if (enter) {
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ARMul_StoreWordN(state, LHS, state->Reg[RHSReg]);
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ARMul_StoreWordN(state,LHS + 4 , state->Reg[RHSReg + 1]);
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state->Reg[DESTReg] = 0;
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} else {
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state->Reg[DESTReg] = 1;
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}
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break;
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}
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#endif
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dest = DPRegRHS;
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WRITEDEST (dest);
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break;
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case 0x1b: /* MOVS reg */
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case 0x1B: /* MOVS reg */
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#ifdef MODET
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/* ldrexd ichfly */
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if (BITS(0, 11) == 0xF9F) { //strexd
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lhs = LHS;
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state->currentexaddr = lhs;
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state->currentexval = (u32)ARMul_ReadWord(state, lhs);
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state->currentexvald = (u32)ARMul_ReadWord(state, lhs + 4);
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state->Reg[DESTReg] = ARMul_LoadWordN(state, lhs);
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state->Reg[DESTReg] = ARMul_LoadWordN(state, lhs + 4);
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break;
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}
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if ((BITS (4, 11) & 0xF9) == 0x9)
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/* LDR register offset, write-back, up, pre indexed. */
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LHPREUPWB ();
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/* Continue with remaining instruction decoding. */
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#endif
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dest = DPSRegRHS;
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WRITESDEST (dest);
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@ -2297,12 +2337,12 @@ mainswitch:
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if (state->currentexval == (u32)ARMul_LoadHalfWord(state, state->currentexaddr))enter = true;
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ARMul_StoreHalfWord(state, lhs, RHS);
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//StoreWord(state, lhs, RHS)
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if (state->Aborted) {
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TAKEABORT;
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}
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if (enter) {
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ARMul_StoreHalfWord(state, lhs, RHS);
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state->Reg[DESTReg] = 0;
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} else {
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state->Reg[DESTReg] = 1;
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@ -2520,7 +2560,7 @@ mainswitch:
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/* TSTP immed. */
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#ifdef MODE32
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state->Cpsr = GETSPSR (state->Bank);
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//ARMul_CPSRAltered (state);
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ARMul_CPSRAltered (state);
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#else
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temp = LHS & DPImmRHS;
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SETR15PSR (temp);
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@ -2547,7 +2587,7 @@ mainswitch:
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/* TEQP immed. */
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#ifdef MODE32
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state->Cpsr = GETSPSR (state->Bank);
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//ARMul_CPSRAltered (state);
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ARMul_CPSRAltered (state);
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#else
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temp = LHS ^ DPImmRHS;
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SETR15PSR (temp);
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@ -2568,7 +2608,7 @@ mainswitch:
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/* CMPP immed. */
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#ifdef MODE32
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state->Cpsr = GETSPSR (state->Bank);
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//ARMul_CPSRAltered (state);
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ARMul_CPSRAltered (state);
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#else
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temp = LHS - DPImmRHS;
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SETR15PSR (temp);
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@ -2604,7 +2644,7 @@ mainswitch:
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/* CMNP immed. */
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#ifdef MODE32
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state->Cpsr = GETSPSR (state->Bank);
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//ARMul_CPSRAltered (state);
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ARMul_CPSRAltered (state);
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#else
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temp = LHS + DPImmRHS;
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SETR15PSR (temp);
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@ -3055,17 +3095,14 @@ mainswitch:
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case 0x68: /* Store Word, No WriteBack, Post Inc, Reg. */
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//ichfly PKHBT PKHTB todo check this
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if ((instr & 0x70) == 0x10) //pkhbt
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{
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if ((instr & 0x70) == 0x10) { //pkhbt
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u8 idest = BITS(12, 15);
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u8 rfis = BITS(16, 19);
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u8 rlast = BITS(0, 3);
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u8 ishi = BITS(7,11);
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state->Reg[idest] = (state->Reg[rfis] & 0xFFFF) | ((state->Reg[rlast] << ishi) & 0xFFFF0000);
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break;
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}
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else if ((instr & 0x70) == 0x50)//pkhtb
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{
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} else if ((instr & 0x70) == 0x50) { //pkhtb
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u8 idest = BITS(12, 15);
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u8 rfis = BITS(16, 19);
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u8 rlast = BITS(0, 3);
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@ -3073,8 +3110,7 @@ mainswitch:
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if (ishi == 0)ishi = 0x20;
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state->Reg[idest] = (((int)(state->Reg[rlast]) >> (int)(ishi))& 0xFFFF) | ((state->Reg[rfis]) & 0xFFFF0000);
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break;
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}
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else if (BIT (4)) {
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} else if (BIT (4)) {
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#ifdef MODE32
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if (state->is_v6
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&& handle_v6_insn (state, instr))
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@ -3686,13 +3722,11 @@ mainswitch:
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/* Co-Processor Data Transfers. */
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case 0xc4:
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if ((instr & 0x0FF00FF0) == 0xC400B10) //vmov BIT(0-3), BIT(12-15), BIT(16-20), vmov d0, r0, r0
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{
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if ((instr & 0x0FF00FF0) == 0xC400B10) { //vmov BIT(0-3), BIT(12-15), BIT(16-20), vmov d0, r0, r0
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state->ExtReg[BITS(0, 3) << 1] = state->Reg[BITS(12, 15)];
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state->ExtReg[(BITS(0, 3) << 1) + 1] = state->Reg[BITS(16, 20)];
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break;
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}
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else if (state->is_v5) {
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} else if (state->is_v5) {
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/* Reading from R15 is UNPREDICTABLE. */
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if (BITS (12, 15) == 15 || BITS (16, 19) == 15)
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ARMul_UndefInstr (state, instr);
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@ -3712,22 +3746,18 @@ mainswitch:
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break;
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case 0xc5:
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if ((instr & 0x00000FF0) == 0xB10) //vmov BIT(12-15), BIT(16-20), BIT(0-3) vmov r0, r0, d0
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{
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if ((instr & 0x00000FF0) == 0xB10) { //vmov BIT(12-15), BIT(16-20), BIT(0-3) vmov r0, r0, d0
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state->Reg[BITS(12, 15)] = state->ExtReg[BITS(0, 3) << 1];
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state->Reg[BITS(16, 19)] = state->ExtReg[(BITS(0, 3) << 1) + 1];
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break;
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}
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else if (state->is_v5) {
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} else if (state->is_v5) {
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/* Writes to R15 are UNPREDICATABLE. */
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if (DESTReg == 15 || LHSReg == 15)
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ARMul_UndefInstr (state, instr);
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/* Is access to the coprocessor allowed ? */
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else if (!CP_ACCESS_ALLOWED(state, CPNum))
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{
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else if (!CP_ACCESS_ALLOWED(state, CPNum)) {
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ARMul_UndefInstr(state, instr);
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}
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else {
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} else {
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/* MRRC, ARMv5TE and up */
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ARMul_MRRC (state, instr, &DEST, &(state->Reg[LHSReg]));
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break;
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@ -4565,7 +4595,7 @@ out:
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#ifdef MODE32
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if (state->Bank > 0) {
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state->Cpsr = state->Spsr[state->Bank];
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//ARMul_CPSRAltered (state);
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ARMul_CPSRAltered (state);
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}
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#ifdef MODET
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if (TFLAG)
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@ -5256,7 +5286,7 @@ L_ldm_s_makeabort:
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//chy 2006-02-16 , should not consider system mode, don't conside 26bit mode
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if (state->Mode != USER26MODE && state->Mode != USER32MODE ) {
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state->Cpsr = GETSPSR (state->Bank);
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//ARMul_CPSRAltered (state);
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ARMul_CPSRAltered (state);
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}
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WriteR15 (state, PC);
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@ -5641,30 +5671,9 @@ L_stm_s_takeabort:
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static int
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handle_v6_insn (ARMul_State * state, ARMword instr) {
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switch (BITS (20, 27)) {
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//ichfly
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case 0x66: //UQSUB8
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if ((instr & 0x0FF00FF0) == 0x06600FF0) {
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u32 rd = (instr >> 12) & 0xF;
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u32 rm = (instr >> 16) & 0xF;
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u32 rn = (instr >> 0) & 0xF;
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u32 subfrom = state->Reg[rm];
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u32 tosub = state->Reg[rn];
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ARMword lhs, temp;
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u8 b1 = (u8)((u8)(subfrom)-(u8)(tosub));
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if (b1 > (u8)(subfrom)) b1 = 0;
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u8 b2 = (u8)((u8)(subfrom >> 8) - (u8)(tosub >> 8));
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if (b2 > (u8)(subfrom >> 8)) b2 = 0;
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u8 b3 = (u8)((u8)(subfrom >> 16) - (u8)(tosub >> 16));
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if (b3 > (u8)(subfrom >> 16)) b3 = 0;
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u8 b4 = (u8)((u8)(subfrom >> 24) - (u8)(tosub >> 24));
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if (b4 > (u8)(subfrom >> 24)) b4 = 0;
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state->Reg[rd] = (u32)(b1 | b2 << 8 | b3 << 16 | b4 << 24);
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return 1;
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} else {
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printf("UQSUB8 decoding fail %08X",instr);
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}
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#if 0
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switch (BITS (20, 27)) {
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case 0x03:
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printf ("Unhandled v6 insn: ldr\n");
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break;
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@ -5678,9 +5687,43 @@ L_stm_s_takeabort:
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printf ("Unhandled v6 insn: smi\n");
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break;
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case 0x18:
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if (BITS(4, 7) == 0x9) {
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/* strex */
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u32 l = LHSReg;
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u32 r = RHSReg;
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lhs = LHS;
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bool enter = false;
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if (state->currentexval == (u32)ARMul_ReadWord(state, state->currentexaddr))enter = true;
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//StoreWord(state, lhs, RHS)
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if (state->Aborted) {
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TAKEABORT;
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}
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if (enter) {
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ARMul_StoreWordS(state, lhs, RHS);
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state->Reg[DESTReg] = 0;
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}
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else {
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state->Reg[DESTReg] = 1;
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}
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return 1;
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}
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printf ("Unhandled v6 insn: strex\n");
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break;
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case 0x19:
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/* ldrex */
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if (BITS(4, 7) == 0x9) {
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lhs = LHS;
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state->currentexaddr = lhs;
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state->currentexval = ARMul_ReadWord(state, lhs);
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LoadWord(state, instr, lhs);
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return 1;
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}
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printf ("Unhandled v6 insn: ldrex\n");
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break;
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case 0x1a:
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@ -5690,9 +5733,52 @@ L_stm_s_takeabort:
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printf ("Unhandled v6 insn: ldrexd\n");
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break;
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case 0x1c:
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if (BITS(4, 7) == 0x9) {
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/* strexb */
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lhs = LHS;
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bool enter = false;
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if (state->currentexval == (u32)ARMul_ReadByte(state, state->currentexaddr))enter = true;
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BUSUSEDINCPCN;
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if (state->Aborted) {
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TAKEABORT;
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}
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if (enter) {
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ARMul_StoreByte(state, lhs, RHS);
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state->Reg[DESTReg] = 0;
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}
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else {
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state->Reg[DESTReg] = 1;
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}
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//printf("In %s, strexb not implemented\n", __FUNCTION__);
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UNDEF_LSRBPC;
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/* WRITESDEST (dest); */
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return 1;
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}
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printf ("Unhandled v6 insn: strexb\n");
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break;
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case 0x1d:
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if ((BITS(4, 7)) == 0x9) {
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/* ldrexb */
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temp = LHS;
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LoadByte(state, instr, temp, LUNSIGNED);
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state->currentexaddr = temp;
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state->currentexval = (u32)ARMul_ReadByte(state, temp);
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//state->Reg[BITS(12, 15)] = ARMul_LoadByte(state, state->Reg[BITS(16, 19)]);
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//printf("ldrexb\n");
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//printf("instr is %x rm is %d\n", instr, BITS(16, 19));
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//exit(-1);
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//printf("In %s, ldrexb not implemented\n", __FUNCTION__);
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return 1;
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}
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printf ("Unhandled v6 insn: ldrexb\n");
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break;
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case 0x1e:
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@ -5713,10 +5799,8 @@ L_stm_s_takeabort:
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case 0x3f:
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printf ("Unhandled v6 insn: rbit\n");
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break;
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#endif
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case 0x61:
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if ((instr & 0xFF0) == 0xf70)//ssub16
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{
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if ((instr & 0xFF0) == 0xf70) { //ssub16
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u8 tar = BITS(12, 15);
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u8 src1 = BITS(16, 19);
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u8 src2 = BITS(0, 3);
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@ -5726,9 +5810,7 @@ L_stm_s_takeabort:
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s16 b2 = ((state->Reg[src2] >> 0x10) & 0xFFFF);
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state->Reg[tar] = ((a1 - a2) & 0xFFFF) | (((b1 - b2) & 0xFFFF) << 0x10);
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return 1;
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}
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else if ((instr & 0xFF0) == 0xf10)//sadd16
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{
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} else if ((instr & 0xFF0) == 0xf10) { //sadd16
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u8 tar = BITS(12, 15);
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u8 src1 = BITS(16, 19);
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u8 src2 = BITS(0, 3);
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@ -5738,9 +5820,7 @@ L_stm_s_takeabort:
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s16 b2 = ((state->Reg[src2] >> 0x10) & 0xFFFF);
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state->Reg[tar] = ((a1 + a2) & 0xFFFF) | (((b1 + b2) & 0xFFFF) << 0x10);
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return 1;
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}
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else if ((instr & 0xFF0) == 0xf50)//ssax
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{
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} else if ((instr & 0xFF0) == 0xf50) { //ssax
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u8 tar = BITS(12, 15);
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u8 src1 = BITS(16, 19);
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u8 src2 = BITS(0, 3);
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@ -5750,9 +5830,7 @@ L_stm_s_takeabort:
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s16 b2 = ((state->Reg[src2] >> 0x10) & 0xFFFF);
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state->Reg[tar] = ((a1 + b2) & 0xFFFF) | (((a2 - b1) & 0xFFFF) << 0x10);
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return 1;
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}
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else if ((instr & 0xFF0) == 0xf30)//sasx
|
||||
{
|
||||
} else if ((instr & 0xFF0) == 0xf30) { //sasx
|
||||
u8 tar = BITS(12, 15);
|
||||
u8 src1 = BITS(16, 19);
|
||||
u8 src2 = BITS(0, 3);
|
||||
|
|
@ -5762,12 +5840,10 @@ L_stm_s_takeabort:
|
|||
s16 b2 = ((state->Reg[src2] >> 0x10) & 0xFFFF);
|
||||
state->Reg[tar] = ((a1 - b2) & 0xFFFF) | (((a2 + b1) & 0xFFFF) << 0x10);
|
||||
return 1;
|
||||
}
|
||||
else printf ("Unhandled v6 insn: sadd/ssub\n");
|
||||
} else printf ("Unhandled v6 insn: sadd/ssub/ssax/sasx\n");
|
||||
break;
|
||||
case 0x62:
|
||||
if ((instr & 0xFF0) == 0xf70)//QSUB16
|
||||
{
|
||||
if ((instr & 0xFF0) == 0xf70) { //QSUB16
|
||||
u8 tar = BITS(12, 15);
|
||||
u8 src1 = BITS(16, 19);
|
||||
u8 src2 = BITS(0, 3);
|
||||
|
|
@ -5783,9 +5859,7 @@ L_stm_s_takeabort:
|
|||
if (res2 < 0x7FFF) res2 = -0x8000;
|
||||
state->Reg[tar] = (res1 & 0xFFFF) | ((res2 & 0xFFFF) << 0x10);
|
||||
return 1;
|
||||
}
|
||||
else if ((instr & 0xFF0) == 0xf10)//QADD16
|
||||
{
|
||||
} else if ((instr & 0xFF0) == 0xf10) { //QADD16
|
||||
u8 tar = BITS(12, 15);
|
||||
u8 src1 = BITS(16, 19);
|
||||
u8 src2 = BITS(0, 3);
|
||||
|
|
@ -5801,200 +5875,124 @@ L_stm_s_takeabort:
|
|||
if (res2 < 0x7FFF) res2 = -0x8000;
|
||||
state->Reg[tar] = ((res1) & 0xFFFF) | (((res2) & 0xFFFF) << 0x10);
|
||||
return 1;
|
||||
}
|
||||
else printf ("Unhandled v6 insn: qadd/qsub\n");
|
||||
} else printf ("Unhandled v6 insn: qadd16/qsub16\n");
|
||||
break;
|
||||
#if 0
|
||||
case 0x63:
|
||||
printf ("Unhandled v6 insn: shadd/shsub\n");
|
||||
break;
|
||||
case 0x65:
|
||||
printf ("Unhandled v6 insn: uadd/usub\n");
|
||||
{
|
||||
u32 rd = (instr >> 12) & 0xF;
|
||||
u32 rn = (instr >> 16) & 0xF;
|
||||
u32 rm = (instr >> 0) & 0xF;
|
||||
u32 from = state->Reg[rn];
|
||||
u32 to = state->Reg[rm];
|
||||
|
||||
if ((instr & 0xFF0) == 0xF10 || (instr & 0xFF0) == 0xF70) { // UADD16/USUB16
|
||||
u32 h1, h2;
|
||||
state->Cpsr &= 0xfff0ffff;
|
||||
if ((instr & 0x0F0) == 0x070) { // USUB16
|
||||
h1 = ((u16)from - (u16)to);
|
||||
h2 = ((u16)(from >> 16) - (u16)(to >> 16));
|
||||
if (!(h1 & 0xffff0000)) state->Cpsr |= (3 << 16);
|
||||
if (!(h2 & 0xffff0000)) state->Cpsr |= (3 << 18);
|
||||
}
|
||||
else { // UADD16
|
||||
h1 = ((u16)from + (u16)to);
|
||||
h2 = ((u16)(from >> 16) + (u16)(to >> 16));
|
||||
if (h1 & 0xffff0000) state->Cpsr |= (3 << 16);
|
||||
if (h2 & 0xffff0000) state->Cpsr |= (3 << 18);
|
||||
}
|
||||
state->Reg[rd] = (u32)((h1 & 0xffff) | ((h2 & 0xffff) << 16));
|
||||
return 1;
|
||||
}
|
||||
else
|
||||
if ((instr & 0xFF0) == 0xF90 || (instr & 0xFF0) == 0xFF0) { // UADD8/USUB8
|
||||
u32 b1, b2, b3, b4;
|
||||
state->Cpsr &= 0xfff0ffff;
|
||||
if ((instr & 0x0F0) == 0x0F0) { // USUB8
|
||||
b1 = ((u8)from - (u8)to);
|
||||
b2 = ((u8)(from >> 8) - (u8)(to >> 8));
|
||||
b3 = ((u8)(from >> 16) - (u8)(to >> 16));
|
||||
b4 = ((u8)(from >> 24) - (u8)(to >> 24));
|
||||
if (!(b1 & 0xffffff00)) state->Cpsr |= (1 << 16);
|
||||
if (!(b2 & 0xffffff00)) state->Cpsr |= (1 << 17);
|
||||
if (!(b3 & 0xffffff00)) state->Cpsr |= (1 << 18);
|
||||
if (!(b4 & 0xffffff00)) state->Cpsr |= (1 << 19);
|
||||
}
|
||||
else { // UADD8
|
||||
b1 = ((u8)from + (u8)to);
|
||||
b2 = ((u8)(from >> 8) + (u8)(to >> 8));
|
||||
b3 = ((u8)(from >> 16) + (u8)(to >> 16));
|
||||
b4 = ((u8)(from >> 24) + (u8)(to >> 24));
|
||||
if (b1 & 0xffffff00) state->Cpsr |= (1 << 16);
|
||||
if (b2 & 0xffffff00) state->Cpsr |= (1 << 17);
|
||||
if (b3 & 0xffffff00) state->Cpsr |= (1 << 18);
|
||||
if (b4 & 0xffffff00) state->Cpsr |= (1 << 19);
|
||||
}
|
||||
state->Reg[rd] = (u32)(b1 | (b2 & 0xff) << 8 | (b3 & 0xff) << 16 | (b4 & 0xff) << 24);
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
printf("Unhandled v6 insn: uasx/usax\n");
|
||||
break;
|
||||
case 0x66:
|
||||
printf ("Unhandled v6 insn: uqadd/uqsub\n");
|
||||
if ((instr & 0x0FF00FF0) == 0x06600FF0) { //uqsub8
|
||||
u32 rd = (instr >> 12) & 0xF;
|
||||
u32 rm = (instr >> 16) & 0xF;
|
||||
u32 rn = (instr >> 0) & 0xF;
|
||||
u32 subfrom = state->Reg[rm];
|
||||
u32 tosub = state->Reg[rn];
|
||||
|
||||
u8 b1 = (u8)((u8)(subfrom)-(u8)(tosub));
|
||||
if (b1 > (u8)(subfrom)) b1 = 0;
|
||||
u8 b2 = (u8)((u8)(subfrom >> 8) - (u8)(tosub >> 8));
|
||||
if (b2 > (u8)(subfrom >> 8)) b2 = 0;
|
||||
u8 b3 = (u8)((u8)(subfrom >> 16) - (u8)(tosub >> 16));
|
||||
if (b3 > (u8)(subfrom >> 16)) b3 = 0;
|
||||
u8 b4 = (u8)((u8)(subfrom >> 24) - (u8)(tosub >> 24));
|
||||
if (b4 > (u8)(subfrom >> 24)) b4 = 0;
|
||||
state->Reg[rd] = (u32)(b1 | b2 << 8 | b3 << 16 | b4 << 24);
|
||||
return 1;
|
||||
} else {
|
||||
printf ("Unhandled v6 insn: uqsub16\n");
|
||||
}
|
||||
break;
|
||||
case 0x67:
|
||||
printf ("Unhandled v6 insn: uhadd/uhsub\n");
|
||||
break;
|
||||
case 0x68:
|
||||
{
|
||||
u32 rd = (instr >> 12) & 0xF;
|
||||
u32 rn = (instr >> 16) & 0xF;
|
||||
u32 rm = (instr >> 0) & 0xF;
|
||||
u32 from = state->Reg[rn];
|
||||
u32 to = state->Reg[rm];
|
||||
u32 cpsr = state->Cpsr;
|
||||
if ((instr & 0xFF0) == 0xFB0) { // SEL
|
||||
u32 result;
|
||||
if (cpsr & (1 << 16))
|
||||
result = from & 0xff;
|
||||
else
|
||||
result = to & 0xff;
|
||||
if (cpsr & (1 << 17))
|
||||
result |= from & 0x0000ff00;
|
||||
else
|
||||
result |= to & 0x0000ff00;
|
||||
if (cpsr & (1 << 18))
|
||||
result |= from & 0x00ff0000;
|
||||
else
|
||||
result |= to & 0x00ff0000;
|
||||
if (cpsr & (1 << 19))
|
||||
result |= from & 0xff000000;
|
||||
else
|
||||
result |= to & 0xff000000;
|
||||
state->Reg[rd] = result;
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
printf("Unhandled v6 insn: pkh/sxtab/selsxtb\n");
|
||||
break;
|
||||
#endif
|
||||
case 0x6c:
|
||||
if ((instr & 0xf03f0) == 0xf0070) //uxtb16
|
||||
{
|
||||
u8 src1 = BITS(0, 3);
|
||||
u8 tar = BITS(12, 15);
|
||||
u32 base = state->Reg[src1];
|
||||
u32 shamt = BITS(9,10)* 8;
|
||||
u32 in = ((base << (32 - shamt)) | (base >> shamt));
|
||||
state->Reg[tar] = in & 0x00FF00FF;
|
||||
return 1;
|
||||
}
|
||||
else
|
||||
printf ("Unhandled v6 insn: uxtb16/uxtab16\n");
|
||||
break;
|
||||
case 0x70:
|
||||
if ((instr & 0xf0d0) == 0xf010)//smuad //ichfly
|
||||
{
|
||||
u8 tar = BITS(16, 19);
|
||||
u8 src1 = BITS(0, 3);
|
||||
u8 src2 = BITS(8, 11);
|
||||
u8 swap = BIT(5);
|
||||
s16 a1 = (state->Reg[src1] & 0xFFFF);
|
||||
s16 a2 = ((state->Reg[src1] >> 0x10) & 0xFFFF);
|
||||
s16 b1 = swap ? ((state->Reg[src2] >> 0x10) & 0xFFFF) : (state->Reg[src2] & 0xFFFF);
|
||||
s16 b2 = swap ? (state->Reg[src2] & 0xFFFF) : ((state->Reg[src2] >> 0x10) & 0xFFFF);
|
||||
state->Reg[tar] = a1*a2 + b1*b2;
|
||||
return 1;
|
||||
|
||||
}
|
||||
else if ((instr & 0xf0d0) == 0xf050)//smusd
|
||||
{
|
||||
u8 tar = BITS(16, 19);
|
||||
u8 src1 = BITS(0, 3);
|
||||
u8 src2 = BITS(8, 11);
|
||||
u8 swap = BIT(5);
|
||||
s16 a1 = (state->Reg[src1] & 0xFFFF);
|
||||
s16 a2 = ((state->Reg[src1] >> 0x10) & 0xFFFF);
|
||||
s16 b1 = swap ? ((state->Reg[src2] >> 0x10) & 0xFFFF) : (state->Reg[src2] & 0xFFFF);
|
||||
s16 b2 = swap ? (state->Reg[src2] & 0xFFFF) : ((state->Reg[src2] >> 0x10) & 0xFFFF);
|
||||
state->Reg[tar] = a1*a2 - b1*b2;
|
||||
return 1;
|
||||
}
|
||||
else if ((instr & 0xd0) == 0x10)//smlad
|
||||
{
|
||||
u8 tar = BITS(16, 19);
|
||||
u8 src1 = BITS(0, 3);
|
||||
u8 src2 = BITS(8, 11);
|
||||
u8 src3 = BITS(12, 15);
|
||||
u8 swap = BIT(5);
|
||||
|
||||
u32 a3 = state->Reg[src3];
|
||||
|
||||
s16 a1 = (state->Reg[src1] & 0xFFFF);
|
||||
s16 a2 = ((state->Reg[src1] >> 0x10) & 0xFFFF);
|
||||
s16 b1 = swap ? ((state->Reg[src2] >> 0x10) & 0xFFFF) : (state->Reg[src2] & 0xFFFF);
|
||||
s16 b2 = swap ? (state->Reg[src2] & 0xFFFF) : ((state->Reg[src2] >> 0x10) & 0xFFFF);
|
||||
state->Reg[tar] = a1*a2 + b1*b2 + a3;
|
||||
return 1;
|
||||
}
|
||||
else printf ("Unhandled v6 insn: smuad/smusd/smlad/smlsd\n");
|
||||
break;
|
||||
case 0x74:
|
||||
printf ("Unhandled v6 insn: smlald/smlsld\n");
|
||||
break;
|
||||
case 0x75:
|
||||
printf ("Unhandled v6 insn: smmla/smmls/smmul\n");
|
||||
break;
|
||||
case 0x78:
|
||||
printf ("Unhandled v6 insn: usad/usada8\n");
|
||||
break;
|
||||
#if 0
|
||||
case 0x7a:
|
||||
printf ("Unhandled v6 insn: usbfx\n");
|
||||
break;
|
||||
case 0x7c:
|
||||
printf ("Unhandled v6 insn: bfc/bfi\n");
|
||||
break;
|
||||
#endif
|
||||
|
||||
|
||||
/* add new instr for arm v6. */
|
||||
ARMword lhs, temp;
|
||||
case 0x18: { /* ORR reg */
|
||||
/* dyf add armv6 instr strex 2010.9.17 */
|
||||
if (BITS (4, 7) == 0x9) {
|
||||
u32 l = LHSReg;
|
||||
u32 r = RHSReg;
|
||||
lhs = LHS;
|
||||
|
||||
bool enter = false;
|
||||
|
||||
if (state->currentexval == (u32)ARMul_ReadWord(state, state->currentexaddr))enter = true;
|
||||
ARMul_StoreWordS(state, lhs, RHS);
|
||||
//StoreWord(state, lhs, RHS)
|
||||
if (state->Aborted) {
|
||||
TAKEABORT;
|
||||
}
|
||||
|
||||
if (enter) {
|
||||
state->Reg[DESTReg] = 0;
|
||||
} else {
|
||||
state->Reg[DESTReg] = 1;
|
||||
}
|
||||
|
||||
return 1;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
case 0x19: { /* orrs reg */
|
||||
/* dyf add armv6 instr ldrex */
|
||||
if (BITS (4, 7) == 0x9) {
|
||||
lhs = LHS;
|
||||
|
||||
state->currentexaddr = lhs;
|
||||
state->currentexval = ARMul_ReadWord(state, lhs);
|
||||
|
||||
LoadWord (state, instr, lhs);
|
||||
return 1;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
case 0x1c: { /* BIC reg */
|
||||
/* dyf add for STREXB */
|
||||
if (BITS (4, 7) == 0x9) {
|
||||
lhs = LHS;
|
||||
|
||||
bool enter = false;
|
||||
|
||||
if (state->currentexval == (u32)ARMul_ReadByte(state, state->currentexaddr))enter = true;
|
||||
|
||||
ARMul_StoreByte (state, lhs, RHS);
|
||||
BUSUSEDINCPCN;
|
||||
if (state->Aborted) {
|
||||
TAKEABORT;
|
||||
}
|
||||
|
||||
|
||||
if (enter) {
|
||||
state->Reg[DESTReg] = 0;
|
||||
} else {
|
||||
state->Reg[DESTReg] = 1;
|
||||
}
|
||||
|
||||
//printf("In %s, strexb not implemented\n", __FUNCTION__);
|
||||
UNDEF_LSRBPC;
|
||||
/* WRITESDEST (dest); */
|
||||
return 1;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
case 0x1d: { /* BICS reg */
|
||||
if ((BITS (4, 7)) == 0x9) {
|
||||
/* ldrexb */
|
||||
temp = LHS;
|
||||
LoadByte (state, instr, temp, LUNSIGNED);
|
||||
|
||||
state->currentexaddr = temp;
|
||||
state->currentexval = (u32)ARMul_ReadByte(state, temp);
|
||||
|
||||
//state->Reg[BITS(12, 15)] = ARMul_LoadByte(state, state->Reg[BITS(16, 19)]);
|
||||
//printf("ldrexb\n");
|
||||
//printf("instr is %x rm is %d\n", instr, BITS(16, 19));
|
||||
//exit(-1);
|
||||
|
||||
//printf("In %s, ldrexb not implemented\n", __FUNCTION__);
|
||||
return 1;
|
||||
}
|
||||
break;
|
||||
}
|
||||
/* add end */
|
||||
|
||||
case 0x6a: {
|
||||
ARMword Rm;
|
||||
int ror = -1;
|
||||
|
|
@ -6023,7 +6021,7 @@ L_stm_s_takeabort:
|
|||
u8 val = BITS(16, 19) + 1;
|
||||
s16 a1 = (state->Reg[src]);
|
||||
s16 a2 = (state->Reg[src] >> 0x10);
|
||||
s16 min = (s16)(0x8000) >> (16 - val);
|
||||
s16 min = (s16)(0x8000 >> (16 - val));
|
||||
s16 max = 0x7FFF >> (16 - val);
|
||||
if (min > a1) a1 = min;
|
||||
if (max < a1) a1 = max;
|
||||
|
|
@ -6056,9 +6054,9 @@ L_stm_s_takeabort:
|
|||
else
|
||||
/* SXTAB */
|
||||
state->Reg[BITS(12, 15)] += Rm;
|
||||
}
|
||||
return 1;
|
||||
|
||||
return 1;
|
||||
}
|
||||
case 0x6b: {
|
||||
ARMword Rm;
|
||||
int ror = -1;
|
||||
|
|
@ -6100,9 +6098,21 @@ L_stm_s_takeabort:
|
|||
else
|
||||
/* SXTAH */
|
||||
state->Reg[BITS(12, 15)] = state->Reg[BITS(16, 19)] + Rm;
|
||||
}
|
||||
return 1;
|
||||
|
||||
return 1;
|
||||
}
|
||||
case 0x6c:
|
||||
if ((instr & 0xf03f0) == 0xf0070) { //uxtb16
|
||||
u8 src1 = BITS(0, 3);
|
||||
u8 tar = BITS(12, 15);
|
||||
u32 base = state->Reg[src1];
|
||||
u32 shamt = BITS(9,10)* 8;
|
||||
u32 in = ((base << (32 - shamt)) | (base >> shamt));
|
||||
state->Reg[tar] = in & 0x00FF00FF;
|
||||
return 1;
|
||||
} else
|
||||
printf ("Unhandled v6 insn: uxtab16\n");
|
||||
break;
|
||||
case 0x6e: {
|
||||
ARMword Rm;
|
||||
int ror = -1;
|
||||
|
|
@ -6158,8 +6168,9 @@ L_stm_s_takeabort:
|
|||
else
|
||||
/* UXTAB */
|
||||
state->Reg[BITS(12, 15)] = state->Reg[BITS(16, 19)] + Rm;
|
||||
}
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
case 0x6f: {
|
||||
ARMword Rm;
|
||||
|
|
@ -6196,7 +6207,8 @@ L_stm_s_takeabort:
|
|||
/* dyf add */
|
||||
if (BITS(16, 19) == 0xf) {
|
||||
state->Reg[BITS(12, 15)] = (Rm >> (8 * BITS(10, 11))) & 0x0000FFFF;
|
||||
} else {
|
||||
}
|
||||
else {
|
||||
/* UXTAH */
|
||||
/* state->Reg[BITS (12, 15)] = state->Reg [BITS (16, 19)] + Rm; */
|
||||
// printf("rd is %x rn is %x rm is %x rotate is %x\n", state->Reg[BITS (12, 15)], state->Reg[BITS (16, 19)]
|
||||
|
|
@ -6206,14 +6218,68 @@ L_stm_s_takeabort:
|
|||
// printf("rd is %x\n", state->Reg[BITS (12, 15)]);
|
||||
// exit(-1);
|
||||
}
|
||||
|
||||
return 1;
|
||||
}
|
||||
case 0x70:
|
||||
if ((instr & 0xf0d0) == 0xf010) { //smuad //ichfly
|
||||
u8 tar = BITS(16, 19);
|
||||
u8 src1 = BITS(0, 3);
|
||||
u8 src2 = BITS(8, 11);
|
||||
u8 swap = BIT(5);
|
||||
s16 a1 = (state->Reg[src1] & 0xFFFF);
|
||||
s16 a2 = ((state->Reg[src1] >> 0x10) & 0xFFFF);
|
||||
s16 b1 = swap ? ((state->Reg[src2] >> 0x10) & 0xFFFF) : (state->Reg[src2] & 0xFFFF);
|
||||
s16 b2 = swap ? (state->Reg[src2] & 0xFFFF) : ((state->Reg[src2] >> 0x10) & 0xFFFF);
|
||||
state->Reg[tar] = a1*a2 + b1*b2;
|
||||
return 1;
|
||||
|
||||
#if 0
|
||||
} else if ((instr & 0xf0d0) == 0xf050) { //smusd
|
||||
u8 tar = BITS(16, 19);
|
||||
u8 src1 = BITS(0, 3);
|
||||
u8 src2 = BITS(8, 11);
|
||||
u8 swap = BIT(5);
|
||||
s16 a1 = (state->Reg[src1] & 0xFFFF);
|
||||
s16 a2 = ((state->Reg[src1] >> 0x10) & 0xFFFF);
|
||||
s16 b1 = swap ? ((state->Reg[src2] >> 0x10) & 0xFFFF) : (state->Reg[src2] & 0xFFFF);
|
||||
s16 b2 = swap ? (state->Reg[src2] & 0xFFFF) : ((state->Reg[src2] >> 0x10) & 0xFFFF);
|
||||
state->Reg[tar] = a1*a2 - b1*b2;
|
||||
return 1;
|
||||
} else if ((instr & 0xd0) == 0x10) { //smlad
|
||||
u8 tar = BITS(16, 19);
|
||||
u8 src1 = BITS(0, 3);
|
||||
u8 src2 = BITS(8, 11);
|
||||
u8 src3 = BITS(12, 15);
|
||||
u8 swap = BIT(5);
|
||||
|
||||
u32 a3 = state->Reg[src3];
|
||||
|
||||
s16 a1 = (state->Reg[src1] & 0xFFFF);
|
||||
s16 a2 = ((state->Reg[src1] >> 0x10) & 0xFFFF);
|
||||
s16 b1 = swap ? ((state->Reg[src2] >> 0x10) & 0xFFFF) : (state->Reg[src2] & 0xFFFF);
|
||||
s16 b2 = swap ? (state->Reg[src2] & 0xFFFF) : ((state->Reg[src2] >> 0x10) & 0xFFFF);
|
||||
state->Reg[tar] = a1*a2 + b1*b2 + a3;
|
||||
return 1;
|
||||
} else printf ("Unhandled v6 insn: smuad/smusd/smlad/smlsd\n");
|
||||
break;
|
||||
case 0x74:
|
||||
printf ("Unhandled v6 insn: smlald/smlsld\n");
|
||||
break;
|
||||
case 0x75:
|
||||
printf ("Unhandled v6 insn: smmla/smmls/smmul\n");
|
||||
break;
|
||||
case 0x78:
|
||||
printf ("Unhandled v6 insn: usad/usada8\n");
|
||||
break;
|
||||
case 0x7a:
|
||||
printf ("Unhandled v6 insn: usbfx\n");
|
||||
break;
|
||||
case 0x7c:
|
||||
printf ("Unhandled v6 insn: bfc/bfi\n");
|
||||
break;
|
||||
case 0x84:
|
||||
printf ("Unhandled v6 insn: srs\n");
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -281,6 +281,7 @@ struct ARMul_State
|
|||
|
||||
ARMword currentexaddr;
|
||||
ARMword currentexval;
|
||||
ARMword currentexvald;
|
||||
ARMword servaddr;
|
||||
|
||||
unsigned NextInstr;
|
||||
|
|
|
|||
|
|
@ -522,8 +522,7 @@ static s64 vfp_single_to_doubleintern(ARMul_State* state, s32 m, u32 fpscr) //ic
|
|||
if (tm == VFP_QNAN)
|
||||
vdd.significand |= VFP_DOUBLE_SIGNIFICAND_QNAN;
|
||||
goto pack_nan;
|
||||
}
|
||||
else if (tm & VFP_ZERO)
|
||||
} else if (tm & VFP_ZERO)
|
||||
vdd.exponent = 0;
|
||||
else
|
||||
vdd.exponent = vsm.exponent + (1023 - 127);
|
||||
|
|
@ -620,7 +619,7 @@ static u32 vfp_single_ftoui(ARMul_State* state, int sd, int unused, s32 m, u32 f
|
|||
if (vsm.exponent >= 127 + 32) {
|
||||
d = vsm.sign ? 0 : 0xffffffff;
|
||||
exceptions = FPSCR_IOC;
|
||||
} else if (vsm.exponent >= 127 - 1) {
|
||||
} else if (vsm.exponent >= 127) {
|
||||
int shift = 127 + 31 - vsm.exponent;
|
||||
u32 rem, incr = 0;
|
||||
|
||||
|
|
@ -705,7 +704,7 @@ static u32 vfp_single_ftosi(ARMul_State* state, int sd, int unused, s32 m, u32 f
|
|||
if (vsm.sign)
|
||||
d = ~d;
|
||||
exceptions |= FPSCR_IOC;
|
||||
} else if (vsm.exponent >= 127 - 1) {
|
||||
} else if (vsm.exponent >= 127) {
|
||||
int shift = 127 + 31 - vsm.exponent;
|
||||
u32 rem, incr = 0;
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue